1. Field
This disclosure relates generally to memory devices, and more specifically, to a split-gate non-volatile memory cell and method.
2. Related Art
For discrete charge split gate memory, a high select gate (SG) threshold voltage (Vt) is required to control leakage and a low control gate (CG) threshold voltage (Vt) is required to control read disturb. Currently, a relatively high substrate doping is used to raise the SG Vt and counterdoping under the CG is used to lower the CG Vt. However, superposing the p- and n-doping under the CG leads to intrinsic doping fluctuations and degraded mobility.
Stated in a different manner, a P-type well doping has been used to control leakage for unselected bitcells. In addition, a high n-type counterdoping implant has been used to compensate for high background p-type well. However, this leads to degraded read current due to low mobility. This also leads to a degraded Vt-window due to strong intrinsic dopant fluctuations. Furthermore, additional Vt variation occurs due to the counterdoping implant. These aspects create limitations on split-gate thin film storage (TFS) bitcell leakage, read current, and Vt-window.
Accordingly, there is a need for an improved method and apparatus for overcoming the problems in the art as discussed above.